1. Field of the Invention
The present invention relates to an improved switch configuration, and in particular an improved switch configuration having an improved power supply rejection ratio (PSRR).
2. Discussion of the Related Art
In order to reduce noise at the output of an amplification system, it is desirable to increase the PSRR (Power Supply Rejection Ratio). The PSRR is a measure of the influence of power supply ripple at the output of the system.
Referring to FIG. 1, a switch 2 has one input node 21 and first and second output nodes 23, 25. The switch operates in one of two states, a first in which the input node 21 is connected to the first output node 23, isolating the input from the second output node 25, and a second state in which the input node 21 is connected to the second output node 25 and is isolated from the first output node 23.
Switch 2 can be implemented using MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) as shown in FIG. 2. With reference to FIG. 2, the switch 2 is shown comprising the input node 21, the first output node 23 and the second output node 25. Switch 2 further comprises a first P-channel MOS transistor 22, connected in parallel with a first N-channel MOS transistor 24, and a second P-channel MOS transistor 26 connected in parallel with a second N-channel MOS transistor 28. The drains of the first and second NMOS transistors 24 and 28 are connected to input node 21, and their sources are connected to first output node 23 and the second output node 25 respectively. The sources of the first and second PMOS transistors 22 and 26 are connected to input node 21, and their drains are connected to the first output node 23 and the second output node 25 respectively. A first switch control signal on a line 30 is connected to the gate node of the first PMOS transistor and second NMOS transistor 22 and 28. A second switch control signal on line 32, which is the inverse of the first switch control signal, is connected to the gates of the second NMOS transistor and first PMOS transistors 24 and 26.
As described above, switch 2 operates in one of two states. In the first state the first switch control signal on line 30 is high and the second switch control signal on line 32 is low, thus turning off first PMOS transistor and NMOS transistors 22 and 24, and turning on second PMOS transistor and NMOS transistors 26 and 28, thereby connecting input node 21 to the second output node 25. In a second state, the first switch control signal on line 30 is low and the second switch control signal on line 32 high, thus turning on first PMOS transistor and NMOS transistors 22 and 24, and turning off second PMOS transistor and NMOS transistors 26 and 28, thereby connecting the input node 21 to the first output node 23.
Switch 2 is disadvantageous due to the parasitic capacitances present between the nodes of the N and P channel MOS transistors. Referring to PMOS transistor 22, a parasitic capacitance 36 is present between the well 34 of PMOS transistor 22 and its drain node, a parasitic capacitance 38 is present between the drain node and the gate node of transistor 22, a parasitic capacitance 40 is present between the gate node and the source node of transistor 22, and a parasitic capacitance 42 is present between the source node and the well 34. NMOS transistor 24 comprises parasitic capacitances 44 and 46 between its gate node and its drain and source respectively. PMOS transistor 26 comprises a well 48, and the same parasitic capacitances, labeled 50 to 56, between adjacent nodes as described above for PMOS transistor 22. NMOS transistor 28 comprises parasitic capacitances 58 and 60 between its gate node and its drain and source respectively.
Combinations of these parasitic capacitances will be present at the input node 21 or the first and second output nodes 23, 25 of the switch when it is in either of the first or second states. Wells 34 and 48 of PMOS transistors 22 and 26 are connected to the noisy supply voltage Vdd, and one of the first and second switch control signals on lines 30 and 32 will always be connected to the noisy supply voltage Vdd in each state of the switch, and thus due to the parasitic capacitances, any ripple in this supply voltage will be present at the input/output nodes of the switch. Particularly in situations in which this switch is used in amplifying circuit arrangements, and the nodes of the switch are connected to inputs of the amplifier, this will result in noise at the output of the system, which is clearly disadvantageous. A high PSRR should therefore be provided for the amplifier system.